DocumentCode
2997147
Title
System partitioning to maximize sleep time
Author
Farrahi, A.H. ; Sarrafzadeh, M.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
fYear
1995
fDate
5-9 Nov. 1995
Firstpage
452
Lastpage
455
Abstract
Partitioning of a system to maximize exploitable sleep time for low-power synthesis is discussed. The motivation is to deactivate the memory refresh circuitry, apply power down or disable the clock signals during the inactive periods of operation of circuit elements, and thus minimize the power consumption. Since it is impractical to have a separate set of control signals for each circuit element (otherwise, the control itself would consume a lot of power), it is advisable to partition a circuit based on the activity patterns of its elements so that the partitions can be switched into sleep mode for long periods of time. In this paper, we formulate this partitioning problem and show that it is NP-hard. We present Geo-Part, a geometric partitioning heuristic for this problem. An efficient implementation of Geo-Part using segment tree data structure is discussed. Experimental results are encouraging.
Keywords
VLSI; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; logic partitioning; Geo-Part; exploitable sleep time; geometric partitioning heuristic; low-power synthesis; memory refresh circuitry; partitioning problem; segment tree data structure; system partitioning; Circuit synthesis; Clocks; Design automation; Digital circuits; Energy consumption; Minimization; Signal synthesis; Sleep; Switching circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-8186-8200-0
Type
conf
DOI
10.1109/ICCAD.1995.480155
Filename
480155
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