Algorithm for Communication Synchronization on Reconfigurable Processor Arrays with Faults

Efficient fault tolerant techniques for reconfigurable multiprocessor array have been extensively studied to construct maximum target array from host array with faulty processors. Existing work focused on the reconfiguration algorithm without considering the communication synchronization of the target array. This paper proposes an algorithm to rearrange the long interconnects of the target array, in order to improve the communication performance in synchronization. In addition, divide and conquer strategy is utilized for deleting logical rows to form a high performance target array with given size. Experimental results show that the proposed algorithm achieves considerable improvement on communication performance in synchronization for the case of small fault rate which is often occurred in real applications.