A Heterogeneous Cache Distribution with Reconfigurable Interconnect

Current trends in multicore research suggest that hundreds of cores will be integrated on a single chip in the near future for increased performance. This new trend presents a set of challenges, one of which is cache distribution among the cores. Network on chip with homogeneous cache distribution among the routers has become mainstream in literature. In this paper, we propose having a heterogeneous distribution of cache blocks to routers. The heterogeneity and the appropriate scheduling by the OS will help to reduce network hops by placing more cache blocks closer to the cores executing data intensive applications. We show that this distribution reduces cache access overhead by as much as 20% percent. Furthermore, we also propose reconfigurable heterogeneous cache architecture for multi-threaded workloads. In this scheme, cache blocks are reassigned to routers based on data needs. A constructive heuristic has been presented which gives the optimal cache configuration and page coloring for each workload. We show that this approach can effectively reduce cache access time by as much as 61% percent.