A new parallel prefix adder structure with efficient critical delay path and gradded bits efficiency in CMOS 90nm technology

In this work we have proposed an efficient parallel prefix adder (PPA) that is a variation of the popular Brent-Kung PPA. In this proposed adder, with a glance on the sklansky adder and by varying the graph topology, we have reduced the number of stages in the critical delay path in comparison with Brent-Kung PPA and so lowered the delay. This advantage is along with a little increase in power consumption and area due to increasing the cells number so that the consequent Power Delay Product (PDP) is improved. Also the performance of our proposed PPA increases by increasing the input bits number from 32 bits up to higher orders. The experimental results indicate that our proposed adder is faster than the Brent-Kung adder by 10.1% in 32 bits, 17.2% in 64 bits and 21.3% in 128 bits and the consequent PDP is reduced by 8.8% in 32 bits, 15.6% in 64 bits and 19.5% in 128 bits. Circuit level simulations were performed with SPICE and CMOS 90nm technology.