A 9.8-10.7 Gb/s Bang-Bang CDR with Automatic Frequency Acquisition Capability

Author

Dodel, Norman ; Klar, Heinrich ; Otte, Sven

Author_Institution

Germany Tech. Univ., Berlin

Volume

2

fYear

2006

fDate

6-9 Aug. 2006

Firstpage

46

Lastpage

49

Abstract

A full-rate bang-bang CDR compliant to SONET OC-192 specifications is presented. The circuit has automatic frequency acquisition capability which is achieved without additional high-speed building blocks. To illustrate the realized frequency acquisition concept, the mechanism which is responsible for acquisition range limitations is explained using a model for a basic bang-bang-PLL in the out-of-lock regime. The test chip was implemented using a 0.25 mum SiGe BiCMOS technology and occupies a die area of 1.5 x 1.5 mm². It has a power dissipation of 363 mW from a 3.3 V supply voltage.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; SONET; phase locked loops; synchronisation; BiCMOS technology; SONET OC-192 specifications; SiGe; automatic frequency acquisition capability; bang-bang CDR; bang-bang-PLL; bit rate 9.8 Gbit/s to 10.7 Gbit/s; frequency acquisition; out-of-lock regime; power 363 mW; size 0.25 mum; voltage 3.3 V; Automatic frequency control; BiCMOS integrated circuits; Circuit testing; Clocks; Phase detection; Phase frequency detector; Phase locked loops; SONET; Sampling methods; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on

Conference_Location

San Juan

ISSN

1548-3746

Print_ISBN

1-4244-0172-0

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2006.382204

Filename

4267282