• DocumentCode
    2998906
  • Title

    A WSI oriented two dimensional systolic array for FFT

  • Author

    Mori, Hideki ; Ouchi, Hiroto ; Mori, Shinichiro

  • Author_Institution
    Toyo University, Kawagoe, Japan
  • Volume
    11
  • fYear
    1986
  • fDate
    31503
  • Firstpage
    2155
  • Lastpage
    2158
  • Abstract
    We consider a new architecture for a WSI (Wafer Scale Integration) oriented FFT processor. A two dimensional systolic array and a parallel FFT algorithm are proposed. The most significant problems are communications, reconfiguration and integrity. Considerations for those problems on WSI are presented. Our new algorithm enables computations of the FFT in parallel in any stage without multidimensional interconnections. Expected performance of the proposed architecture is also discussed.
  • Keywords
    Arithmetic; Clustering algorithms; Communication system control; Computer architecture; Concurrent computing; Fault tolerance; Hardware; Multidimensional systems; Systolic arrays; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
  • Type

    conf

  • DOI
    10.1109/ICASSP.1986.1168627
  • Filename
    1168627
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2998906