Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS

Author

Sadhu, B. ; Sturm, Martin ; Sadler, B.M. ; Harjani, Ramesh

Author_Institution

University of Minnesota, Minneapolis,

Volume

48

Issue

5

fYear

2013

fDate

May-13

Firstpage

1199

Lastpage

1211

Abstract

This work describes the design of a 16 point analog domain FFT using a Charge Re-use Analog Fourier Transform (CRAFT) engine. The circuit relies on charge re-use to achieve 47 dB average output SNDR on an instantaneous input bandwidth of 5 GHz, and consumes only 3.8 mW (12.2 pJ/conv.). The CRAFT engine is used as a wide-band, low power RF front-end channelizer for software defined radio (SDR) applications. The paper also discusses the handling of circuit non-idealities for the CRAFT design: their significance, modeling, and circuit techniques for their mitigation. These techniques enable this implementation to achieve a large dynamic range even at high speeds.

Keywords

Analytical models; FET integrated circuits; FIR filters; MOS integrated circuits; OFDM; RF signals; analog integrated circuits; channel bank filters; cognitive radio; demodulation; discrete Fourier transforms; discrete cosine transforms; fast Fourier transforms; filtering; integrated circuit modeling; integrated circuit noise; linear circuits; mixed analog digital integrated circuits; modulation; multiple signal classification; multiplying circuits; passive circuits; passive filters; phase shifters; radio spectrum management; radio-frequency integrated circuits; sampled data circuits; signal analysis; signal detection; signal sampling; signal to noise ratio; software defined radio; software radio; spectral analysis; summing circuits; switched capacitor; switched circuits; transforms; very high speed integrated circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2013.2250457

Filename

6506133