Power Optimization in Low-Voltage High-Speed High-Resolution Pipelined ADCs

Low-power design of low-voltage high-speed high-resolution A/D converters is presented. By expressing the total current consumption of the ADC as well as the ADC noise power as functions of the stage resolutions, the stage capacitors and the compensation capacitors of the cascode-compensated opamps, all those parameters are optimally determined in order to minimize power consumption for a definite budget for the noise power. In this methodology, the small-signal settling is considered as well as the large-signal settling. Besides, the contribution of the comparators is considered in the entire ADC current consumption. At last two power-optimized pipelined ADCs utilizing the proposed and conventional design methods are presented and compared in 0.18 mum CMOS technology with 1.2 V supply voltage. Considerable reduction in power consumption is achieved.