TMS 320C25 based enhanced 32 kbps ADPCM transcoder

The CCITT recommendation, G.721 for a 64 kbps PCM to 32 kbps ADPCM transcoder algorithm does not easily lend itself to implementation on general purpose digital signal processors. The authors present a bit-for-bit compatible realization of the algorithm and a functional real time test bed for algorithm modifications. The hardware of the unit, USF32-2 is built around a single TMS320C25 microprocessor and has added circuitry to decrease computation time and facilitate testing. The base algorithm and enhanced version can be selectively compared. The encoder/decoder requires a total of 1301 clock cycles, but can be compressed to 1250, thereby enabling one to run both the encoder and the decoder on a single TMS320C25 processor