Algorithmic Design of High-Precision Low-Power Multi-Stage Decimation Filters

An algorithm for design of high-precision low- power decimation filters for DeltaSigma analog-to-digital converters is described. This algorithm has been applied to decimation filters with oversampling ratios of 32 to 256, passband ripples of 2 to 0.0003 dB, stopband attenuation of -30 to -120 dB, and passband edge of 0.35 fs to 0.454 fs, where fs is the output sampling rate. This paper then goes forward by presenting a multiplierless, low- power multi-stage digital filter for decimation in DeltaSigma converters. A four-stage decimation filter with down-sampling factor of 64 is developed. A multi-stage CIC (Cascaded Integrator-Comb) filter which reduces the sampling rate by 8 is used for the first stage. Two halfband filters and an FIR droop correction filter follow the CIC filter each reducing the sampling rate by two. Techniques to simultaneously achieve high performance and low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than -120 dB and the passband ripple is less than 0.0003 dB. The designed decimation filter is synthesized on standard cells of a 0.18 mum CMOS library. The designed and synthesized decimation filter contributes to a power consumption saving of 10.6% compared to the previous successful filters implemented on the same library.