A non-slicing floorplanning algorithm using corner block list topological representation

Corner Block List (CBL)-a new efficient topological representation for a non-slicing floorplan is proposed with applications to VLSI floorplan and building block placement. Given a CBL, it takes only linear time to construct the floorplan. CBL defines the floorplan independent of the block size, so the structure is better suited to floorplan optimization with various size configurations of each block. Based on this new structure and the simulated annealing technique, an efficient floorplan algorithm is given. Soft blocks, the aspect ratio of the chip and boundary constraints are taken into account in the simulated annealing process. The experimental results demonstrate the algorithm is quite promising