DocumentCode :
2999808
Title :
APPlaUSE: area and performance optimization in a unified placement and synthesis environment
Author :
Frank, O. ; Lengauer, T.
Author_Institution :
German Nat. Res. Center for Inf. Technol, St. Augustin, Germany
fYear :
1995
fDate :
5-9 Nov. 1995
Firstpage :
662
Lastpage :
667
Abstract :
We present a new methodology for high-level synthesis, which incorporates placement in an early phase of the synthesis process. This placement, prior to interconnect and storage allocation, allows for early and accurate estimates on area and net length. These cost factors are critical for the quality of the chip. The system has been implemented and extensive tests verify the estimates to be accurate.
Keywords :
circuit CAD; circuit layout; circuit layout CAD; circuit optimisation; high level synthesis; APPlaUSE; area optimization; cost factors; high-level synthesis; performance optimization; placement; placement and synthesis environment; Circuit synthesis; Circuit testing; Costs; Hardware; High level synthesis; Information technology; Optimization; Registers; Routing; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-8186-8200-0
Type :
conf
DOI :
10.1109/ICCAD.1995.480200
Filename :
480200
Link To Document :
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