Title :
Fully planar 0.562μm2 T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMs
Author :
Nemati, Farid ; Cho, Hyun-Jin ; Robins, Scott ; Gupta, Rajesh ; Tarabbia, Marc ; Yang, Kevin J. ; Hayes, Dennis ; Gopalakrishnan, Vasudevan
Author_Institution :
T-RAM Inc., San Jose, CA, USA
Abstract :
Major advancements in T-RAM cell manufacturability are reported. A fully planar implementation of a T-RAM cell is presented, which is easily integrated into a baseline 130nm SOI CMOS logic technology by adding photo-mask and ion-implantation steps. The cell area of 0.562μm2 (33F2) is four times smaller than conventional 6T-SRAM. A new scheme, called Restore, significantly improves control of the cell standby current. Excellent T-RAM cell temperature stability is demonstrated between 0°C and 125°C. Measurement results from a 9Mb T-RAM test chip with full SRAM functionality show good bit yield, 2ns cell write speed, 1.7ns cell read speed, and a cell standby current of ∼1nA/cell.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; circuit stability; integrated circuit manufacture; ion implantation; masks; nanotechnology; silicon-on-insulator; 0 to 125 C; 1.7E-9 s; 130 nm; 2E-9 s; SOI CMOS logic technology; SRAM functionality; T-RAM cell manufacturability; T-RAM test chip; bit yield; cell read speed; cell standby current; cell write speed; fully planar T-RAM cell; high-density SRAM; ion-implantation; photo-mask; temperature stability; CMOS logic circuits; CMOS technology; Current measurement; Manufacturing; Random access memory; Semiconductor device measurement; Stability; Temperature; Testing; Velocity measurement;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419130
