Truncated Multiplications for the Negative Two´s Complement Number System

In the design of digital signal processing systems, where single-precision results are required, the power dissipation and area of parallel multipliers can be significantly reduced by truncating the less significant columns and compensating to produce an approximate rounded product. This paper provides the design and modeling of truncated multiplications of signed inputs utilizing the negative fractional two´s complement number system and compares them with those for the unsigned number system and the conventional two´s complement number system. A software simulation finds the input patterns with extreme errors for truncated multiplication with constant correction. It is shown that the negative two´s complement number system is suitable for truncated multiplication of signed numbers.