Map channel decoding: Algorithm and VLSI architecture

Author

Dawid, Herbert ; Gehnen, Gerrit ; Meyr, Heinrich

Author_Institution

Aachen Univ. of Technol., Germany

fYear

1993

fDate

20-22 Oct 1993

Firstpage

141

Lastpage

149

Abstract

The symbol by symbol MAP algorithm is parallelized leading to a purely feedforward block processing architecture for high speed soft output channel decoding. Using a novel algebraic formulation of the MAP algorithm, an algorithmic modification is discussed resulting a large decrease in complexity. A concatenated decoding system employing the soft output MAP algorithm compares favorably with parallel Viterbi decoders using a standard code, which is proved by a high speed system example

Keywords

CMOS logic circuits; VLSI; Viterbi decoding; application specific integrated circuits; channel coding; concatenated codes; digital signal processing chips; feedforward; maximum likelihood decoding; parallel algorithms; parallel architectures; CMOS; algorithmic modification; concatenated decoding system; decrease in complexity; feedforward block processing architecture; high speed; maximum a posteriori; parallel VLSI architectures; parallelized; single chip; soft output channel decoding; symbol MAP algorithm; Code standards; Concatenated codes; Convolutional codes; Maximum likelihood decoding; Maximum likelihood estimation; Probability; Recursive estimation; Shift registers; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, VI, 1993., [Workshop on]

Conference_Location

Veldhoven

Print_ISBN

0-7803-0996-0

Type

conf

DOI

10.1109/VLSISP.1993.404493

Filename

404493