A topology-based method for identifying flip-flop graphs in BJT circuits

Author

Vargas Bernal, R. ; Reyes, Arturo Sirmiento

Author_Institution

Dept. of Electron., Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico

Volume

6

fYear

1999

fDate

36342

Firstpage

133

Abstract

This paper presents a method focused on finding embedded flip-flop graphs in circuit topology. The method is based on performing a tearing of the graph of the dead network. It is implemented in a methodological way by applying a series of graph operations. The method is applied to networks containing BJTs, independent current and voltage sources, and positive linear resistors but it can be easily modified to cope with other kinds of active devices

Keywords

active networks; bipolar transistor circuits; flip-flops; graph theory; network topology; nonlinear network analysis; BJT circuits; Schmitt triggers; active devices; circuit topology; dead network; embedded flip-flop graphs; flip-flop graphs identification; graph tearing; independent current and voltage sources; nonlinear resistive circuit; positive linear resistors; square matrix; topology-based method; Bipolar transistor circuits; Bonding; Circuit stability; Circuit topology; Coupling circuits; Ear; Flip-flops; Nonlinear optics; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780113

Filename

780113