A Robust High-Speed Chaos-Based Truly Random Number Generator for Embedded Cryptosystems

This paper presents a high-speed truly random number generator based on a simple chaotic map of the Bernoulli shift, which is extended to keep robustness in practical implementation. The design is realized by switched- current techniques that can make it be fully integrated in embedded cryptosystems. And a pipelined architecture post- processed by a SHA-1 hardware module is proposed to improve the throughput and the randomness statistical properties. The whole design is implemented in UMC 0.18 mum CMOS mixed signal process, and the statistical properties are investigated by post-simulations. The power consumption is low and the truly random output bit rate can get to 266 Mbit/s.