Analysis on data retention time of nano-scale DRAM and its prediction by probing the tail cell leakage current

Author

Lee, W.S. ; Lee, S.H. ; Lee, C.-S. ; Lee, K.-H. ; Kim, H.-J. ; Kim, J.-Y. ; Yang, W. ; Park, Y.K. ; Kong, J.-T. ; Ryu, B.-I.

Author_Institution

Semicond. R&D Center, Samsung Electron. Co., Ltd., Gyeonggi-Do, South Korea

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

395

Lastpage

398

Abstract

Characteristics of the data retention time (tRET) of nano-scale DRAM have been described. In addition, new approaches to enhance tRET and their properties have been analyzed. To optimize the process, we developed the tRET-modeling methodology, which has a good agreement with experimental data. The key feature of the methodology is an indirect probing of the tail leakage current by fitting the leakage model to reproduce the measured characteristics of the retention. The model shows the GIDL current is a major factor determining tRET of 80nm RCAT technology.

Keywords

DRAM chips; integrated circuit modelling; leakage currents; nanoelectronics; GIDL current; RCAT technology; data retention time; indirect probing; nano-scale DRAM; tRET-modeling methodology; tail cell leakage current; Computer aided engineering; Data analysis; Doping; Implants; Leakage current; Optimization methods; Predictive models; Random access memory; Research and development; Tail;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419168

Filename

1419168