DocumentCode :
3001347
Title :
A Proposed Fast Word Level Sequential Scheme and Parallel Architecture for Bit Plane Coding of EBCOT Used in JPEG2000
Author :
Fang, Qi ; Zhang, Weijiang ; Pang, Zhiyong ; Chen, Dihu ; Wang, Zixin
Author_Institution :
Sch. of Phys. & Eng., Sun Yat-sen Univ., Guangzhou, China
fYear :
2010
fDate :
29-31 Oct. 2010
Firstpage :
1
Lastpage :
4
Abstract :
Bit Plane Coding (BPC) is an important component of the EBCOT block in JPEG2000 encoder. This paper introduced new algorithm for neighboring significance contribution and Run Length Coding (RLC). The paper also presented a fast word level sequential scheme and parallel architecture for bit plane coding. Bit plane coding adopted by EBCOT is mainly divided into three stages: significance generation, coding pass prediction and context formation, which work in parallel and pipelined. The proposed architecture simplifies control procedure and operates at a higher processing speed (up to 164MHz in Xilinx Virtex 4 FPGA).
Keywords :
image coding; EBCOT block; JPEG2000 encoder; Xilinx Virtex 4 FPGA; bit plane coding; coding pass prediction; fast word level sequential scheme; parallel architecture; run length coding; Algorithm design and analysis; Complexity theory; Context; Encoding; Image coding; Pipelines; Transform coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multimedia Technology (ICMT), 2010 International Conference on
Conference_Location :
Ningbo
Print_ISBN :
978-1-4244-7871-2
Type :
conf
DOI :
10.1109/ICMULT.2010.5630940
Filename :
5630940
Link To Document :
بازگشت