Title :
A high speed CMOS/SOS implementation of a bit level systolic correlator
Author :
White, J.C. ; McCanny, J.V. ; McCabe, A. ; McWhirter, J. ; Evans, R.
Author_Institution :
Marconi Electronic Devices, Lincoln
Abstract :
The fabrication and performance of the first bit level systolic correlator array is described. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64 stage correlation for 1 bit reference and 4 bit data.
Keywords :
Adders; Circuits; Computer architecture; Correlators; Fabrication; Matrix decomposition; Pipelines; Signal processing; Systolic arrays; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
DOI :
10.1109/ICASSP.1986.1168833
