A delay efficient robust self-timed full adder

Addition forms the basis of digital computer systems. A gate level self-timed full adder design, utilizing a pre-defined set of gates, available in a commercial synchronous standard cell library is discussed in this paper. The proposed adder satisfies Seitz´s weak-indication specifications and exhibits reduced data path delay in comparison with other existing adders, which satisfy the property of indication. In terms of power and area, it is competitive to the best of other self-timed adders.