Title :
DSP implementation and performances evaluation of 1D and 2D DWT using the lifting scheme
Author :
Ben Hnia Gazzah, I. ; Souani, Chokri ; Besbes, Kamel
Author_Institution :
Lab. Microelectron. et Instrum., Fac. des Sci. de Monastir, Monastir
Abstract :
This paper presents the implementation of a lifting scheme-based DWT architecture on a digital signal processor (DSP) (TMS320C6713) core and the simulation using MATLAB. The 5/3 and 9/7 wavelet filters used in JPEG 2000 are both implanted and executed by the DSP processor for comparisons. The algorithms proposed are optimized at source code level and memory usage. The execution time for performing both DWTs is measured for 1D and 2D-DWT for different number of level, depending on on-chip and off-chip memory.
Keywords :
digital filters; digital signal processing chips; discrete wavelet transforms; image coding; source coding; 1D DWT architecture; 2D DWT architecture; DSP processor implementation; JPEG 2000; MATLAB; TMS320C6713 core; lifting scheme; off-chip memory; on-chip memory; source code level; wavelet filters; Convolution; Digital signal processing; Discrete wavelet transforms; Filter bank; Image coding; Low pass filters; MATLAB; Performance evaluation; Time measurement; Transform coding;
Conference_Titel :
Design and Test Workshop, 2008. IDT 2008. 3rd International
Conference_Location :
Monastir
Print_ISBN :
978-1-4244-3479-4
Electronic_ISBN :
978-1-4244-3478-7
DOI :
10.1109/IDT.2008.4802490
