DocumentCode :
3003533
Title :
A new cell-based performance metric for novel CMOS device architectures
Author :
Christie, P. ; Heringa, A. ; Doornbos, G. ; Kumar, A. ; Nguyen, V.H. ; Ng, R.K.M. ; Garg, Mayank
Author_Institution :
Philips Res., Leuven, Belgium
fYear :
2004
fDate :
13-15 Dec. 2004
Firstpage :
743
Lastpage :
746
Abstract :
This paper introduces, for the first time, a method for assessing the impact of CMOS technology choices on dynamic system level performance. The method is applied to the evaluation of five different device architectures, which include bulk, FDSOI, and multi-gate devices. Timing and power information at the standard cell level is extracted for each of the devices and used to simulate their performance embedded within a cell array of 230,400 cells.
Keywords :
CMOS integrated circuits; silicon-on-insulator; CMOS device architectures; FDSOI; dynamic system level performance; multigate devices; Algorithm design and analysis; CMOS technology; Capacitance; Delay; Measurement; Medical simulation; Routing; Timing; Voltage; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
Type :
conf
DOI :
10.1109/IEDM.2004.1419279
Filename :
1419279
Link To Document :
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