Title :
Edge trapping mechanism of current collapse in III-N FETs
Author :
Braga, N. ; Mickevicius, R. ; Gaska, R. ; Shur, M.S. ; Khan, M.Asif ; Simin, G.
Author_Institution :
Integrated Syst. Eng. Inc., San Jose, CA, USA
Abstract :
Simulations of GaN HFETs using the device simulator DESSIS show, in agreement with our experimental data, that enhanced trapping at both gate edges is responsible for the current collapse. These simulations also show a reduction of the collapse in DHFETs with an InGaN channel, in agreement with our gated transmission line measurements. The results demonstrate that hot electrons play an instrumental role in the collapse process.
Keywords :
III-V semiconductors; electron traps; field effect transistors; gallium compounds; hot carriers; indium compounds; semiconductor device models; wide band gap semiconductors; DESSIS; DHFET; III-N FET; InGaN; InGaN channel; current collapse; device simulator; edge trapping mechanism; enhanced trapping; gate edges; gated transmission line measurement; heterojunction field effect transistor; hot electrons; semiconductor device simulations; Electrical resistance measurement; FETs; HEMTs; MESFETs; MODFETs; MOSFETs; MOSHFETs; Modeling; Stress; Transmission line measurements;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419300
