Author :
Cea, S.M. ; Armstrong, M. ; Auth, C. ; Ghani, T. ; Giles, M.D. ; Hoffmann, T. ; Kotly, R. ; Matagne, P. ; Mistry, K. ; Nagisetty, R. ; Obradovic, B. ; Shaheed, R. ; Shifren, L. ; Stettler, M. ; Yagi, S.T. ; Wang, X. ; Weber, Charles ; Zawadzki, K.
Author_Institution :
Technol. CAD, Intel Corp., Hillsboro, OR, USA
Abstract :
This paper presents an integrated approach to modeling front end stress which has been used to investigate the main sources of stress in advanced logic technologies and how they can be used to improve device performance. The approach is illustrated with the evaluation of several technologically important stress options.
Keywords :
Ge-Si alloys; electronic engineering computing; integrated circuit design; internal stresses; logic devices; stress analysis; thermal stresses; SiGe; advanced logic technology; device performance; front end stress modeling; stress simulations; Capacitive sensors; Elasticity; Logic; Semiconductor device modeling; Semiconductor process modeling; Silicon; Solid modeling; Tensile stress; Thermal stresses; Viscosity;
