Multiplier architecture for digital filters

Since multipliers are the slowest and most expensive components in digital filters, schemes for increasing speed and reducing cost are of interest. For a device that does multiplication by successive shift and add operations, different architectures can be used to speed the process and allow for hardware sharing. Several architectures are discussed in this paper. For filters that carry a small digital word length, nonconventional multiply schemes may well be appropriate. Two such schemes, table look up and residue algebra, are discussed herein.