Title :
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
Author :
Yang, H.S. ; Malik, R. ; Narasimha, S. ; Li, Y. ; Divakaruni, R. ; Agnello, P. ; Allen, S. ; Antreasyan, A. ; Arnold, J.C. ; Bandy, K. ; Belyansky, M. ; Bonnoit, A. ; Bronner, G. ; Chan, V. ; Chen, X. ; Chen, Z. ; Chidambarrao, D. ; Chou, A. ; Clark, W. ;
Author_Institution :
IBM Syst. & Technol. Group, Hopewell Junction, NY, USA
Abstract :
For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.
Keywords :
CMOS integrated circuits; delays; field effect transistors; hole mobility; integrated circuit technology; integrated circuit yield; silicon-on-insulator; DSL process yield; SOI CMOS manufacturing; compressively stress; drive current enhancement; dual stress liner; high performance CMOS flow; hole mobility enhancement; inverter ring oscillator delay; multi-core SOI microprocessors; nitride contact liners; single core SOI microprocessors; sub-45nm gate length; tensile stress; Compressive stress; DSL; Delay; Germanium silicon alloys; Inverters; Manufacturing; Microprocessors; Ring oscillators; Silicon germanium; Tensile stress;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419385
