Architectural considerations for a sub 10 nanosecond DSP building block family

A recently announced bipolar VLSI fabrication process provides high-speed ECL gates with substantially lower power dissipation and smaller device sizes. This combination can implement a 16 × 16 bit multiplier array with a delay time of less than 10 nanoseconds, less than 2 watts power dissipation and a silicon area comparable to 1.5 micron CMOS of 16.3K sq. mils. This paper will discuss the architectural considerations of applying this new technology to a family of fixed-point VLSI building blocks for digital signal processing applications.