DocumentCode
3006830
Title
Enhanced Buck-Boost Three-Level Neutral-Point-Clamped Inverters
Author
Tan, K.K. ; Gao, F. ; Loh, P.C. ; Blaabjerg, Frede
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ.
fYear
2009
fDate
15-19 Feb. 2009
Firstpage
689
Lastpage
695
Abstract
In traditional three-level neutral-point-clamped (NPC) inverters, a major issue is capacitor voltage imbalance, which results in low order harmonics. The compensation of the capacitor voltages often require additional control complexity, which cannot be conveniently implemented. The "alternative phase opposition disposition" (APOD) modulation method used in traditional NPC topologies also has lower harmonics performance as compared to the "phase disposition" (PD) modulation method. In this paper, we introduce a new three-level NPC topology that utilises the harmonically superior PD modulation method, with the ability to easily adjust for capacitor voltage imbalances. To further improve the boost capability of the three-level NPC inverters, another new topology introduces 2 additional diodes, achieving higher boost performance while totally eliminating the possibility of capacitor voltage mismatch.
Keywords
capacitors; invertors; voltage control; alternative phase opposition disposition modulation method; capacitor voltage imbalance; capacitor voltages compensation; enhanced buck-boost clamped inverters; low order harmonics; three-level neutral-point-clamped inverters; Capacitors; Circuit topology; Diodes; Network topology; Optimal control; Performance loss; Phase modulation; Pulse width modulation inverters; Renewable energy resources; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Power Electronics Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual IEEE
Conference_Location
Washington, DC
ISSN
1048-2334
Print_ISBN
978-1-4244-2811-3
Electronic_ISBN
1048-2334
Type
conf
DOI
10.1109/APEC.2009.4802735
Filename
4802735
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