Pulse-triggered flip-flop design with PTL style control scheme

In this paper, a novel low power pulse-triggered flip-flop design is presented. Firstly, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple 2-transistor AND gate design is used to reduce the circuit complexity. Secondly, a conditional pulse enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse generation circuit can be reduced for power saving. Various post-layout simulation results based on UMC CMOS 90nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate based FF design, the average leakage power consumption is also reduced by a factor of 3.52.