Title :
ASAver.1: an FPGA-based education board for computer architecture/system design
Author_Institution :
Dept. of Comput. Eng., Hiroshima Univ., Japan
Abstract :
This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a pipelined RISC processor within limited time available for the course. The approach consists of 4 steps; at the first step, modeling of pipelined RISC processor is simplified by avoiding structural hazard and by ignoring other hazards, and in the succeeding steps, students learn difficulties of pipelining by themselves. An educational FPGA board ASAver.1 and results of feasibility study are also shown
Keywords :
computer aided instruction; computer architecture; computer science education; electronic engineering education; field programmable gate arrays; pipeline processing; reduced instruction set computing; systems analysis; ASAver.1; FPGA-based education board; computer architecture; pipelined RISC processor; structural hazard; system design; Computer architecture; Computer displays; Computer science education; Field programmable gate arrays; Hardware; Hazards; Microprocessors; Pipeline processing; Reduced instruction set computing; Switches;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600102