Synchronous performance and reliability improvement in pipelined ASICs

The clock frequency of a synchronous circuit can be increased at the expense of increased system latency, area, and power using synchronous optimization techniques such as pipelining and retiming. Pipelining is well developed methodology, having been applied to almost every computer architecture from microprocessors to supercomputers. Retiming, on the other hand, has only recently become popular and practical application areas currently being developed. Both pipelining and retiming are reviewed in this paper. In order to make retiming more generally useful, low-level circuit delay components inherent to IC must be incorporated into the retiming process. These include variable register delay, clock skew, and interconnect delay. An algorithm is presented by the authors for incorporating variable register delays, interconnect delay, and the clock skew into retiming. The algorithm identifies and eliminates path-dependant race conditions in synchronous circuits. The results of applying the algorithm to MCNC benchmarks is presented and both performance and reliability improvements are observed