Title :
Characterization of opens in logic circuits
Author :
Rogenski, Jeffrey S. ; Ferguson, F. Joel
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
We present an algorithm for extracting opens in rectilinear circuit layouts using a plane-sweep technique. An implementation of the algorithm is used to characterize realistic opens in combinational circuit layouts. The occurrence of three types of opens possible in standard cells is examined. The number of single and multiple stuck-at faults due to opens in benchmark circuits is determined, assuming that floating nodes cause stuck-at faults. The distribution of open critical area between cells and routing, and between circuit layers is measured for the benchmark circuits
Keywords :
CMOS logic circuits; circuit analysis computing; combinational circuits; fault diagnosis; integrated circuit layout; logic testing; combinational circuit layouts; logic circuits; opens extraction; plane-sweep technique; rectilinear circuit layouts; standard cells; stuck-at faults; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Conducting materials; Joining processes; Logic circuits; Manufacturing processes; Probability; Routing;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404541
