• DocumentCode
    3010140
  • Title

    Design Proposal for a Chip Jointing VLSI and Rat Spinal Cord Neurons on a Single Silicon Wafer

  • Author

    Liu, Zihong ; Wang, ZhiHua ; Li, GuoLin ; Yu, Zhiping ; Zhang, Chun

  • Author_Institution
    Dept. of Electron. Eng., Tsinghua Univ., Beijing
  • fYear
    2005
  • fDate
    16-19 March 2005
  • Firstpage
    158
  • Lastpage
    161
  • Abstract
    The high complexity of live beings´ nervous system determines it´s difficult to analyze the working principles of such behaviors as thinking, learning and cognition at molecular level today, i.e. the development of artificial neural networks (ANN) still has to be limited by the understanding of biological neuron networks (BNN). As of now, several studies on neuron-silicon hybrids have been evolved and shown primary success and led to a new emerging multidisciplinary field. In this paper, we propose a novel hybrid neural system chip jointing rat spinal cord neurons and large-scale integrated circuits (VLSI) on a single silicon wafer substrate for fast signal recognition, where three modules are designed and interconnected. Recorded simulations show that combining the individual advantages of BNN and VLSI, the chip will have more intelligent and faster signal processing capabilities as compared with traditional ANN method, especially for fuzzy signals. Moreover, it can also resolve the problems of huge memory space in ANN chips and the high complexity for algorithms
  • Keywords
    VLSI; electroencephalography; elemental semiconductors; fuzzy control; medical signal processing; neural nets; neurophysiology; silicon; Si; VLSI; artificial neural networks; biological neuron networks; cognition; hybrid neural system chip jointing; large-scale integrated circuits; learning; nervous system; neuron-silicon hybrids; rat spinal cord neurons; signal processing; signal recognition; single silicon wafer; thinking; Artificial neural networks; Cognition; Large scale integration; Nervous system; Neurons; Proposals; Signal processing algorithms; Silicon; Spinal cord; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Neural Engineering, 2005. Conference Proceedings. 2nd International IEEE EMBS Conference on
  • Conference_Location
    Arlington, VA
  • Print_ISBN
    0-7803-8710-4
  • Type

    conf

  • DOI
    10.1109/CNE.2005.1419578
  • Filename
    1419578