A current-mode continuous-time ΣΔ modulator with delayed return-to-zero feedback

Author

Aboushady, H. ; Mendes, E. DaLira ; Dessouky, M. ; Loumeau, P.

Author_Institution

Paris VI Univ., France

Volume

2

fYear

1999

fDate

36342

Firstpage

360

Abstract

In this paper, a design method for continuous-time ΣΔ modulators with RZ feedback pulse is proposed. This method is used to design a second-order continuous-time ΣΔ modulator. The circuit is realized using continuous-time current-mode integrators and switched-current sources DAC. The effect of the integrator thermal noise and nonideal RZ feedback pulse on the system performance is studied. An analog layout language was used to generate the complete layout of the modulator in a 0.6 μm CMOS process. With a sampling frequency of 28 MHz, the circuit is expected to achieve 80 dB of dynamic range for a 200 kHz bandwidth input signal. The circuit operates from a power supply of ±1.65 V with a power consumption of 9.1 mW and occupies an area of 0.348 mm²

Keywords

CMOS integrated circuits; circuit feedback; circuit layout CAD; continuous time systems; current-mode circuits; integrated circuit layout; integrated circuit noise; integrating circuits; sigma-delta modulation; thermal noise; -1.65 to 1.65 V; 200 kHz; 26 MHz; 9.1 mW; CMOS; analog layout language; current-mode continuous-time ΣΔ modulator; current-mode integrators; delayed return-to-zero feedback; dynamic range; integrator thermal noise; power consumption; sampling frequency; second-order modulator; CMOS process; Circuit noise; Design methodology; Dynamic range; Feedback; Frequency; Pulse modulation; Signal sampling; Switching circuits; System performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780733

Filename

780733