Bipolar ESD power clamp in high voltage CMOS based on TCAD device simulation

The paper contributes a specific way to form bipolar ESD power clamp in high voltage CMOS technologies. The CMOS technology cannot use efficient bipolar structures but only the parasitic structures. Here, the functional ESD power clamp is introduced which has higher holding voltage than conventional structures in CMOS. The higher holding voltage is very necessary for power clamps. The structure were formed and simulated in TCAD device simulator and manufactured in high voltage CMOS process.