DocumentCode
3010899
Title
RICK: A DFT advisor for digital circuit design
Author
Dholakia, Ajay
Author_Institution
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fYear
1991
fDate
24-26 Sep 1991
Firstpage
393
Lastpage
398
Abstract
Design for testability (DFT) requires digital circuit designers to address the issues of testability during the design phase. To simplify this task, a number of knowledge-based DFT expert systems have been suggested. A DFT advisor which can offer testability advice to the designer at all the stages of the design phase is described. It is implemented using the constraint programming language Galileo
Keywords
automatic testing; circuit CAD; digital circuits; expert systems; RICK; concurrent engineering; constraint programming language Galileo; design for testability; digital circuit design; knowledge based expert system; Area measurement; Circuit synthesis; Circuit testing; Costs; Design engineering; Design for testability; Digital circuits; Knowledge based systems; System testing; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
AUTOTESTCON '91. IEEE Systems Readiness Technology Conference. Improving Systems Effectiveness in the Changing Environment of the '90s, Conference Record.
Conference_Location
Anaheim, CA
Print_ISBN
0-87942-576-8
Type
conf
DOI
10.1109/AUTEST.1991.197582
Filename
197582
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