• DocumentCode
    301104
  • Title

    A scalable cache design for I-structures in multithreaded architectures

  • Author

    Gaudiot, Jean-Luc ; Cheng, Chung-Ta

  • Author_Institution
    Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
  • Volume
    1
  • fYear
    1996
  • fDate
    12-16 Aug 1996
  • Firstpage
    263
  • Abstract
    I-Structures were originally proposed to handle producer-consumer parallelism in data-driven execution models. Although they provide fine-grain synchronization and non-strict execution capability, they do not exploit data locality, usually a key factor in performance improvement. In this paper, we propose a novel cache design for I-Structures in a multithreaded multiprocessor. It can exploit both temporal and spatial locality without any of the associated cache coherence costs. A highly scalable method for storing the deferred requests is employed, which further facilitates the processing of deferred requests in a parallel and distributed fashion
  • Keywords
    cache storage; data structures; parallel architectures; I-structures; cache coherence costs; cache design; data locality; data-driven execution models; deferred requests; fine-grain synchronization; multithreaded architectures; nonstrict execution capability; performance improvement; producer-consumer parallelism; scalable cache design; spatial locality; temporal locality; Cache memory; Concurrent computing; Costs; Data structures; Functional programming; Parallel machines; Parallel processing; Parallel programming; Programming profession; Scalability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing, 1996. Vol.3. Software., Proceedings of the 1996 International Conference on
  • Conference_Location
    Ithaca, NY
  • ISSN
    0190-3918
  • Print_ISBN
    0-8186-7623-X
  • Type

    conf

  • DOI
    10.1109/ICPP.1996.537168
  • Filename
    537168