Title :
Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation
Author :
Kouretas, I. ; Paliouras, V.
Author_Institution :
Electrical and Computer Engineering Dept., University of Patras, Greece
Abstract :
In this paper the utilization of Residue Number System (RNS) is investigated as a tool for variation-tolerant design. In particular circuits using various RNS bases are compared to the equivalent binary structures in terms of their sensitivity to the variation of process parameters. Furthermore, RNS advantages are quantitatively illustrated by considering a timing model with two non-gaussian distributions. It is shown that for bases where all moduli channels are candidates to contain the critical path of the RNS circuit, the delay variation is significantly reduced when compared to the equivalent binary structures.
Keywords :
Logic gates; RNS; Residue arithmetic; arithmetic circuits; variation-tolerant design;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271458