Current mode multiple-valued adder for cryptography processors

This paper presents the design and implementation of a multiple-valued adder, with application in smart cards and cryptographic processors. The adder is designed based on the principles of truncated Continuous Valued Number System (CVNS), in order to relax the implementation requirements of the circuit topology and designs. The CVNS adder has an almost constant power consumption, independent of the input values. This feature makes this adder immune against side channel attacks, which may use the power consumption pattern to obtain the intermediate values of arithmetic operations.