A framework to study time-dependent variability in circuits at sub-35nm technology nodes

This paper presents a framework to investigate the potential impact of time-dependent variability at future technology nodes. Both static statistical variability and NBTI-induced device degradation have been integrated to represent the time-dependent variability, and the impact on the performance of an ISCAS benchmark circuit in sub-35nm technologies has been studied. The BSIM4 compact models of MOSFET at 25, 18 and 13nm nodes are calibrated by a 3D atomistic device simulator with chip measurements of 35nm gate length devices. Synthesis results confirm that the variability of circuit performance will increase as device scaling continues, and can be more severe in new circuits at 18nm than in those stressed for a period of three years at 35nm. In addition, the results also reveal that increasing power consumption as adopted in adaptive supply voltage (ASV) and adaptive back bias (ABB) schemes is not a sustainable solution to compensate the drift in performance for future generations of CMOS circuits and systems.