• DocumentCode
    3015243
  • Title

    Low-complexity parallel evaluation of powers exploiting bit-level redundancy

  • Author

    Abbas, Muhammad ; Gustafsson, Oscar ; Blad, Anton

  • Author_Institution
    Dept. of Electr. Eng., Linkoping Univ., Linköping, Sweden
  • fYear
    2010
  • fDate
    7-10 Nov. 2010
  • Firstpage
    1168
  • Lastpage
    1172
  • Abstract
    In this work, we investigate the problem of computing any requested set of power terms in parallel using summations trees. This problem occurs in applications like polynomial approximation, Farrow filters (polynomial evaluation part) etc. In the proposed technique, the partial product of each power term is initially computed independently. A redundancy check is then made in each and among all partial products matrices at bit level. The redundancy here relates to the fact that same three partial products may be present in more than one columns, and, hence, can be mapped to the same full adder. The proposed algorithm is tested for different sets of powers and wordlengths to exploit the sharing potential.
  • Keywords
    adders; digital arithmetic; matrix algebra; redundancy; trees (mathematics); Farrow filter; bit level redundancy; full adder; low complexity parallel evaluation; partial product matrix; polynomial approximation; power terms; summation tree; Adders; Digital signal processing; Encoding; Polynomials; Redundancy; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA
  • ISSN
    1058-6393
  • Print_ISBN
    978-1-4244-9722-5
  • Type

    conf

  • DOI
    10.1109/ACSSC.2010.5757714
  • Filename
    5757714