DocumentCode
3015783
Title
Volume and power optimized high-performance system for UAV collision avoidance
Author
Nagy, Zoltán ; Kiss, András ; Zarándy, Ákos ; Zsedrovits, Tamás ; Vanek, Bálint ; Peni, Tamas ; Bokor, József ; Roska, Tamás
Author_Institution
Computer and Automation Research Institute of the Hungarian Academy of Sciences (MTA-SZTAKI), Budapest, Hungary
fYear
2012
fDate
20-23 May 2012
Firstpage
189
Lastpage
192
Abstract
An on-board UAV high-performance collision avoidance system sets up drastic constraints, which can be fulfilled by using carefully optimized many-core computational architectures. We report here a case study, where we implemented a many-core processor system, which can process a 100 megapixels/sec video flow, identifying remote airplanes, tracking flying objects by implementing computationally intensive Kalman filters. The introduced processor system is implemented in Spartan 6 FPGA, and consumes less than 1W.
Keywords
Clocks; Collision avoidance; Computer architecture; Field programmable gate arrays; Gray-scale; Power demand;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location
Seoul, Korea (South)
ISSN
0271-4302
Print_ISBN
978-1-4673-0218-0
Type
conf
DOI
10.1109/ISCAS.2012.6271640
Filename
6271640
Link To Document