A Highly-Stable Nanometer Memory for Low-Power Design

Author

Lin, Sheng ; Kim, Yong-Bin ; Lombardi, Fabrizio

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA

fYear

2008

fDate

29-30 Sept. 2008

Firstpage

17

Lastpage

20

Abstract

A nine transistor (9T) cell at a 32nm feature size in CMOS is proposed to accomplish improvements in stability as well as power dissipation compared with previous designs for low-power memory operation. Initially, this paper shows that the proposed 9T SRAM cell can be used for robust, high-density design. Then, an optimum sizing is found for this 9T cell by considering stability, energy consumption, and performance. A write bitline balancing scheme is proposed to further reduce the power consumption of the SRAM cell. The impact of process variations is investigated in detail, and the power reduction of the 9T SRAM cell is verified under parameter variations.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit design; low-power electronics; transistors; CMOS; SRAM cell; highly-stable nanometer memory; low-power memory operation; nine transistor cell; write bitline balancing scheme; Circuit testing; Conferences; Energy consumption; Leakage current; Nanoscale devices; Power supplies; Random access memory; Stability; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test of Nano Devices, Circuits and Systems, 2008 IEEE International Workshop on

Conference_Location

Cambridge, MA

Print_ISBN

978-0-7695-3379-7

Type

conf

DOI

10.1109/NDCS.2008.10

Filename

4638326