Title :
FSM synthesis on FPGA architectures
Author :
Sarwary, C. ; Lopes, E. Prado ; Burgun, L. ; Greiner, A.
Author_Institution :
Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
Abstract :
We present a new approach for FSM synthesis on the two most popular FPGA architectures: Actel and Xilinx. This approach deals with state assignment, optimization and mapping problems. Very fast FPGA mapping techniques based on multi-ROBDD representation (Shared, Reduced and Ordered BDDs) have been defined that allow the target architecture to be really taken into consideration during all the phases of the synthesis, A prototype has been developed for FSM synthesis on Xilinx X3090 and Actel ACT1 architectures. The results are promising when compared with traditional approaches implemented by Sis
Keywords :
Boolean functions; circuit optimisation; field programmable gate arrays; finite state machines; logic CAD; state assignment; Actel; FPGA architectures; FSM synthesis; Xilinx; circuit optimization; mapping problems; multi-ROBDD representation; state assignment; target architecture; Boolean functions; Cost function; Data structures; Delay; Encoding; Field programmable gate arrays; Logic; Network synthesis; Prototypes; State estimation;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404581
