• DocumentCode
    3017587
  • Title

    Generation of optimum test stimuli for nonlinear analog circuits using nonlinear programming and time-domain sensitivities

  • Author

    Burdiek, Bernhard

  • Author_Institution
    Inst. fur Theor. Elektrotechnik, Hannover Univ., Germany
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    603
  • Lastpage
    608
  • Abstract
    In this paper a novel approach for the generation of an optimum transient test stimulus for general analog circuits is proposed. The test stimulus is optimal with respect to the detection of a given fault set by means of a predefined fault detection criterion. The problem of finding an optimum test stimulus detecting all faults from the fault set is formulated as a nonlinear programming problem. A functional describing the differences between the good and all faulty test responses of the circuit serves as a merit functional for the programming problem. A parameter vector completely describing the test stimulus is used as the optimization vector. The gradient of the merit functional required for the optimization is computed using time-domain sensitivities. Since in this approach the evaluation of the fault detection criterion represented by the merit functional flows directly into the computation of the test stimulus, optimal test stimuli for hard to detect faults can be generated. If more than one input terminal is used for testing, several test stimuli can be generated simultaneously
  • Keywords
    analogue integrated circuits; automatic testing; circuit optimisation; fault diagnosis; integrated circuit testing; nonlinear network analysis; nonlinear programming; fault set; merit functional; nonlinear analog circuits; nonlinear programming; optimization vector; optimum test stimuli; parameter vector; predefined fault detection criterion; test responses; time-domain sensitivities; transient test stimulus; Analog circuits; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fault detection; Functional programming; Integrated circuit testing; Sequential analysis; Time domain analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
  • Conference_Location
    Munich
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-0993-2
  • Type

    conf

  • DOI
    10.1109/DATE.2001.915085
  • Filename
    915085