Partial Gating Optimization for Power Reduction During Test Application

Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to block transitions from propagating from the outputs of scan cells through combinational logic. In order to accomplish this, some authors have proposed the setting of primary inputs to appropriate values or adding extra gates at the outputs of scan cells. In this paper, we point out the limitations of such full gating technique. We propose an alternate solution where a partial set of scan cells is gated. The subset of scan cells is selected to give maximum reduction in test power within a given area constraint. An alternate formulation of the problem is to treat maximum permitted test power and area overhead as constraints and achieve a test power that is within these limits using the fewest number of gated scan cells, thereby leading to least impact in area overhead. Our problem formulation also comprehends performance constraints and prevents the inclusion of gating points on critical paths. The area overhead is predictable and closely corresponds to the average power reduction.