Title :
Enhancing simulation with BDDs and ATPG
Author :
Ganai, Malay K. ; Aziz, Adnan ; Kuehlmann, Andreas
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
We introduce SImulation Verification with Augmentation (SIVA), a tool for checking safety properties on digital hardware designs. SIVB integrates simulation with symbolic techniques for vector generation. Specifically, the core algorithm uses a combination of ATPG and BDDs to generate input vectors which cover behavior not excited by simulation. Experimental results demonstrate considerable improvement in state space coverage compared with either simulation or formal verification in isolation
Keywords :
automatic test pattern generation; binary decision diagrams; combinational circuits; finite state machines; formal verification; high level synthesis; logic simulation; reachability analysis; ATPG; BDD; RTL description; SIVA tool; backtrack limits; core algorithm; digital hardware designs; enhanced simulation; finite state machine; reachability analysis; safety properties; simulation verification with augmentation; state space coverage; symbolic techniques; vector generation; Automatic test pattern generation; Boolean functions; Computational modeling; Computer bugs; Data structures; Formal verification; Hardware; Permission; Safety; Testing;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781346
