DocumentCode
302000
Title
RF to digital direct conversion receiver using PLL-Σ/Δ architecture: possibilities and problems
Author
Zhu, Lizhong ; Vlach, Jiri
Author_Institution
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Volume
1
fYear
1996
fDate
12-15 May 1996
Firstpage
449
Abstract
The possibilities and problems of using PLL-Σ/Δ architecture to construct a RF to digital direct conversion receiver is investigated by taking different kinds of noises into consideration. The contribution of each noise in the receiver is analyzed by deriving the output response of the receiver in the z-domain and performing time-domain simulation. Some preliminary results are given
Keywords
circuit noise; phase locked loops; radio receivers; sigma-delta modulation; time-domain analysis; PLL-Σ/Δ architecture; RF to digital direct conversion receiver; noise; output response; time-domain simulation; z-domain; Active noise reduction; Baseband; Computer architecture; Filters; Noise figure; Phase locked loops; Phase modulation; Phase noise; RF signals; Radio frequency;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.539981
Filename
539981
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