DocumentCode
3020150
Title
High quality analog CMOS and mixed signal LSI design
Author
Matsuzawa, Akira
Author_Institution
Div. of Corp. Semicond. Dev., Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fYear
2001
fDate
2001
Firstpage
97
Lastpage
104
Abstract
This paper presents an overview of high quality design methodology both in the analog CMOS and in the mixed signal LSI. The important design considerations in analog CMOS are first discussed. Not only taking the conventional methodology into account but also taking care of the process fluctuation, including VT mismatch or 1/f noise, leading to robust and high quality analog CMOS circuits. For the rapid-growing high frequency applications, parasitic effects such as cross-coupled capacitance and substrate power loss are becoming serious issues. Thus it is demonstrated that pre- and post-layout simulations are vital to achieve target characteristics. The mixed signal LSI design today requires system-level simulation in order to meet the competitive performance specifications. The mixed-mode simulation, using SPICE, Verlog-D, and Verilog-A, which can concurrently handle analog and digital circuits, is shown to be essential to the overall mixed signal system design. The substrate noise or EMI need to be analyzed effectively under such an environment as well. Finally, accurate device parameter extraction, its careful reflection to above circuit designs, and fine parameter control in manufacturing for the active and passive devices are described
Keywords
1/f noise; CMOS analogue integrated circuits; VLSI; capacitance; circuit CAD; circuit simulation; integrated circuit design; integrated circuit noise; large scale integration; mixed analogue-digital integrated circuits; EMI; SPICE; SoC design; Verilog-A; Verlog-D; accurate device parameter extraction; analog CMOS design; cross-coupled capacitance; fine parameter control; high quality IC design; high quality design methodology; mixed-mode simulation; mixed-signal LSI design; parasitic effects; performance specifications; post-layout simulations; pre-layout simulations; process fluctuation; substrate noise; substrate power loss; system-level simulation; system-on-chip design; CMOS analog integrated circuits; CMOS process; Circuit noise; Circuit simulation; Design methodology; Fluctuations; Frequency; Large scale integration; Noise robustness; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2001 International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-1025-6
Type
conf
DOI
10.1109/ISQED.2001.915212
Filename
915212
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